The field of the invention is integrated circuit processing, in particular forming interconnect structures in the back end or the first metal contact in the front end.
In the course of manufacturing integrated circuits, many tests are performed to verify that the process is within its design parameters. In addition, reliability tests are performed to verify the durability or reliability of the product under stress and time. Preferably, the tests are performed in real time i.e. the result is available immediately. The longer the interval between the construction process and the test result, the longer the time in which the process will continue to be out of specification before it is corrected.
One test that is routinely performed is a “burn-in” test, in which the complete working circuit is placed in a chamber at an elevated temperature while it is operated. The elevated temperature (typically about 140 degrees Centigrade) accelerates chemical reactions and the product degradation, as well as putting thermal stress on mechanical joints, so that the failure rate is accelerated.
This test assesses the performance of the completed circuit and therefore requires that the circuit be completed. The length of time that it takes for a circuit to pass through the back end steps of a fabrication facility is approximately 3–4 months. Thus, this test is not suitable for monitoring the status of an individual step in the process. By the time a step that is out of specification or reliability standard is detected, a large number of lots will have passed through the manufacturing fab and been processed with the incorrect step. Since the circuit has been completed, it is not practical to rework the defective step i.e. removing the layers that were put on after the defective step, re-doing the step in question, and then re-doing all the later steps is not practical.
Various methods of getting results with a shorter turn-around are known, but have various drawbacks.
In one method, a wafer is taken from the line, cut in sections and examined under an electron microscope. This gives a result that reflects the actual state of the process, but is limited to only a few samples and permanently destroys the wafer being tested.
U.S. Pat. No. 4,881,591, for example, illustrates a burn-in oven for performing a thermal stress test. Such a test stresses the circuit and accelerates chemical reactions, so that potential corrosion effects happen much sooner than in actual use, but the results are much too slow to be useful in monitoring the actual state of the parameters on a production line.
U.S. Pat. No. 6,278,129 shows a scheme in which special test structures outside the die are fabricated on a wafer, that are sensitive to corrosion. The structures are tested during the passage of the wafer through the fab to reveal problems caused by the harsh chemicals used in processing. The test structures that are designed to be more sensitive than the real structure and may not be exactly representative of the actual structures in the circuits being fabricated.
The art has long sought a quick test that measures the reliability of the actual structures in the circuit.